1. Field of the Invention
This invention pertains generally to semiconductor memory, and more particularly to control circuits within dynamic random access memories.
2. Description of Related Art
Dynamic Random Access Memory (DRAM) has been used as a main memory for servers, personal computers, and a wide range of other electronic devices. During DRAM operation a core sensing operation that reads data from the memory cell is key to determining DRAM access speed and minimum operating voltage. Lowering the operating voltage is very important for current and future applications to achieve power savings and device scalability. However, operation at reduced voltages inevitably causes performance (speed) degradation of the transistor due to the smaller gate-to-source voltage (VGS) available. Currently, the only way to mitigate such performance degradation is to scale down the threshold voltage of the transistor. However, the scaling of the threshold voltage also causes an exponential increase in the sub-threshold leakage current flowing through the transistor even though the transistor is in an off state.
This sub-threshold leakage current can constitute a substantial portion of the overall power consumption, in particular power consumption in the standby mode. Typically, the maximum standby current in the self-refresh mode of the DRAM is about 100 μA. When the transistor with the scaled threshold voltage (i.e., low Vt transistor) is utilized, a typical sub-threshold leakage current for a 0.13 μm technology is about 10 nA and can reach about 1 μA when subjected to an elevated temperature such as 125° C. Typically, the sense amplifier is shared by two bit lines in different blocks and 256 cells are connected to the bit line in each block (256 cells per bit line). Therefore, for a 1 Gigabit DRAM having 1024×1024×1024 cells, there are 2×1024×1024 sense amplifiers. If the sub-threshold leakage current per sense amplifier is 1 nA (10−9 A), the total sub-threshold leakage current is 2×1024×1024×10−9=2 mA, which is much larger than the maximum allowable standby current in the self-refresh mode.
FIG. 1 and FIG. 2 depict a conventional DRAM core structure and its associated timing diagram. Typically, the DRAM device is implemented with a folded-bit line structure as shown in the figure. The memory array consists of plural word lines and bit lines. In FIG. 1, there are 256 word lines and 256 bit line pairs. Since there is one cell per bit line pair in the folded-bit line architecture, the memory array size is 256×256=64 k bit. The bit line sense amplifier is placed per bit line pair, thus there are 256 sense amplifiers in this memory array. The typical structure of sense amplifier used in DRAM is a CMOS latch sense amplifier, such as comprising transistors mns1_1, mns1_2, mps1_1 and mps1_2 with source nodes comprising source node sensing (SAN) and source node restoring (SAP), connected with those of other sense amplifiers. That is, the SAN and SAP nodes of the first bit line pair (BL1 and BLB1) are connected with SAN and SAP nodes of the second bit line pair (BL2 and BLB2) and the 256th bit line pair (BL256 and BLB256) as shown in FIG. 1. The source transistors, mpsrc and mnsrc, are generally located per 256 bit line pairs as depicted in FIG. 1. The number of bit line pairs where source transistors are located depends on DRAM design. For example, the source transistors can be placed per four bit line pairs and the nodes, SAN and SAP, are connected with more bit line pairs, such as connecting with 256 bit line pairs.
The operation of the conventional DRAM core is as follows. In precharge state, bit line pairs are precharged to half VDD through equalization transistors, mne1_1, mne1_2 and mne1_3 for the first bit line pair. Voltage VBL is an internal voltage source to provide half VDD voltage to bit line pairs.
In active mode, line PEQ goes low and all equalization transistors are turned off. A word line in the memory block goes to voltage VPP which exceeds voltage VDD and provides a voltage which is at least equal to VDD plus Vtn, where Vtn is the threshold voltage of the cell access transistor, such as transistor mnc1_1 for the one bit line pair. It is assumed that line WL1 goes to voltage VPP in response to the input address. There is a charge-sharing operating between cell (CS1_1) and bit line capacitance (CBL_1). The bit line capacitance is a parasitic capacitance composed of junction and line capacitance. In the following description it is assumed that stored data at the cell is at logic high. After the charge sharing operation, a certain voltage is developed on the bit line, BL1, which is equal to (CS1_1/(CS1_1+CBL_1))×VDD/2.
Then, a signal goes to logic high to turn on a drain of NMOS source transistor mnsrc and the signal developed on the bit line is amplified in response to the latching arrangement of NMOS transistors mns1_1 and mns1_2. Later, the other drain of PMOS source transistor mpsrc is turned-on to restore cell data based on the latching arrangement of PMOS transistors mps1_1 and mps1_2. So, the levels of signals SA_BL1 and SA_BLB1 become VDD and VSS, respectively, when the sensing operation is completed. Since the NMOS transistor is used to isolate the blocks that share the sense amplifier, the PISO signal goes to a boosted voltage, VPP, to avoid a Vt drop by the NMOS transistors, mniso1_1.
Therefore, the logic high data can be transferred to line BL1 without signal degradation and restored once again into the cell. Similarly, the sensing operation is performed for all bit lines that have cells activated by the word line.
After cell data is read out and restored, the word line is shut off. Signals, PSAE and PSAEB return to logic low and high, respectively, to turn off the source transistors of bit line sense amplifier. Then, signal PEQ goes to high to make the levels of bit lines equalized to half VDD (VDD/2). This chip then again enters into so-called precharge state.
In precharge state, since the source transistors of bit line sense amplifiers are turned-off, theoretically, there is no current flowing from VDD to VSS. However, due to the device characteristics of MOS transistors, leakage current exists and such a leakage current can represent a large portion of total current draw as the device is scaled down as explained above.
Another drawback of conventional dynamic memory core circuits involves the delay caused by charge sharing when using high voltage threshold transistors in the data access circuit. This drawback is partially met using a negative word line scheme as depicted in FIG. 3, in which a word line level is set to a voltage lower than voltage VSS when the cell is not accessed.
Additional drawbacks can be found in conventional dynamic memory core circuits which consume unnecessary power or unduly lengthen access times.
Accordingly, a need exists for memory implementations which provide improved speed while suppressing sub-threshold leakage current, and other forms of excess power consumption. The present invention satisfies those needs, as well as others, and overcomes the deficiencies of previously developed memory architectures and sense amplifiers.